// Texas A&M University          //
// cpsc350 Computer Architecture //
// $Id: mux.v,v 1.1 2001/11/07 19:24:39 miket Exp miket $ //
// Multiplexers of various bit-sizes and input to output mapping //
module MUX32_2to1(a0, a1, sel, out);
   input [31:0] a0, a1;
   input 	sel;
   output [31:0] out;
   reg [31:0] 	 out;
   
   always @(a0 or a1 or sel)
      if (sel == 0) out = a0;
      else          out = a1;
endmodule // MUX32_2to1

// TODO: add delay!
module MUX32_32to1(a0, a1, a2, a3, a4, a5, a6, 
				   a7, a8, a9, a10, a11, a12,
				   a13, a14, a15, a16, a17, a18, 
				   a19, a20, a21, a22, a23, a24,
				   a25, a26, a27, a28, a29, a30,
				   a31, // inputs
				   sel, out);
		
	input [31:0] a0, a1, a2, a3, a4, a5, a6, 
				   a7, a8, a9, a10, a11, a12,
				   a13, a14, a15, a16, a17, a18, 
				   a19, a20, a21, a22, a23, a24,
				   a25, a26, a27, a28, a29, a30,
				   a31;
    input [4:0] sel;
	output [31:0] out;
	reg [31:0] out;
	
	always@(sel or a0 or a1 or a2 or a3 or a4 or a5 or a6 or 
				   a7 or a8 or a9 or a10 or a11 or a12 or
				   a13 or a14 or a15 or a16 or a17 or a18 or 
				   a19 or a20 or a21 or a22 or a23 or a24 or
				   a25 or a26 or a27 or a28 or a29 or a30 or
				   a31)
	begin
	  case(sel)
	    5'd0: assign out = a0;
		5'd1: assign out = a1;
	    5'd2: assign out = a2;
		5'd3: assign out = a3;
		5'd4: assign out = a4;
		5'd5: assign out = a5;
		5'd6: assign out = a6;
		5'd7: assign out = a7;
		5'd8: assign out = a8;
		5'd9: assign out = a9;
		5'd10: assign out = a10;
		5'd11: assign out = a11;
		5'd12: assign out = a12;
		5'd13: assign out = a13;
		5'd14: assign out = a14;
		5'd15: assign out = a15;
		5'd16: assign out = a16;
		5'd17: assign out = a17;
		5'd18: assign out = a18;
		5'd19: assign out = a19;
		5'd20: assign out = a20;
		5'd21: assign out = a21;
		5'd22: assign out = a22;
		5'd23: assign out = a23;
		5'd24: assign out = a24;
		5'd25: assign out = a25;
		5'd26: assign out = a26;
		5'd27: assign out = a27;
		5'd28: assign out = a28;
		5'd28: assign out = a29;
		5'd30: assign out = a30;
		5'd31: assign out = a31;		
	  endcase	
	end
		
endmodule

module MUX32_3to1(a0, a1, a2, sel, out);
   input [31:0] a0, a1, a2;
   input [1:0] 	sel;
   output [31:0] out;
   reg [31:0] 	 out;
   
   always @(a0 or a1 or a2 or sel)
      if (sel == 0) out = a0;
      else if (sel == 1) out = a1;
	   else out = a2;
endmodule // MUX32_3to1


module MUX5_2to1(a0, a1, sel, out);
   input [4:0]  a0, a1;
   input 	sel;
   output [4:0] out;
   reg [4:0] 	out;
   
   always @(a0 or a1 or sel)
      if (sel == 0) out = a0;
      else          out = a1;
endmodule // MUX5_2to1


